For every succeeding generation of integrated circuits, both transistor speed and transistor density has increased. To increase the transistor density, the metal line widths, via diameters, and spacing for the electrical interconnects have been reduced. The reduction of metal line width and via diameter increases the electrical resistance of these structures, while reduction of the spacing increases the capacitance between the metal lines. These two factors combine to decrease the switching speed of the interconnect, thus reducing the frequency at which the integrated circuit can reliably operate. Therefore, the design goal of increasing the density of an integrated circuit tends to be odds with the design goal of increasing the speed of the integrated circuit.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
Two methods have been investigated to overcome these competing design problems. The first is to replace the aluminum, that was traditionally used for the metal interconnects, with copper. Copper has a lower bulk resistivity than aluminum, and therefore is a better conductor. By making this replacement, smaller interconnects could be fashioned, having the same resistance as the older aluminum interconnects.
The second method is to replace the silicon oxide, that was traditionally used for the dielectric insulation between the metal interconnects, with a low k material. Low k materials have a lower dielectric constant than silicon oxide, and therefore a layer of a low k material induces less capacitance between adjacent metal lines than does a layer of silicon oxide. By making this replacement, smaller spacing between interconnects could be fashioned, having no more capacitance than the older silicon oxide dielectrics.
Unfortunately, these solutions have proven to be inadequate for a variety of reasons. For example, as device geometries continue to decrease, even copper, with its lower resistivity, is still too resistive for the desired new interconnect dimensions. Further, low k materials are notoriously fragile, and tend to not provide the structural strength required by the integrated circuit. This problem is made worse when the amount of low k material is reduced as the spacing between the electrically conductive interconnects is reduced.
What is needed, therefore, is a system that overcomes problems such as those described above, at least in part.